This invention relates to an information reproduction system adapted to reduce the rate of faulty code reproduction due to address errors in reproducing codes that are optically readably recorded according to a predetermined block arrangement format for information data that comprise block data obtained by dividing the information data by a given data volume and block headers allocated to the respective blocks to show their addresses.
The assignee of the present invention proposed an information recording/reproduction system for recording digital data on a recording medium and reproducing the recorded data as described in Patent Publication EP 0,670,555 A1 (which corresponds to U.S. Ser. No. 80/407,018).
With a system as proposed in the above patent document, data are divided into blocks, each having a predetermined data volume, and an address data is affixed to each of the blocks. For reproducing the data, the block data of each of the blocks are read out with the address affixed thereto and all the read out block data are combined according to the addresses to reproduce the original data. Thus, with the characteristic feature of dividing data into blocks and affixing an address to each of the blocks, the system is highly adapted to data expansion and shows an enhanced level of flexibility for reading data. For example, the data picked up by the system as an image can be read by scanning the codes in the image no matter how densely the data are arranged in the image and even if the blocks are arranged at random and the image is scanned manually at a varying scanning speed to give rise to a blurred effect.
While the use of block addresses is highly effective, sufficient care and measures should be taken not to miss any of them.
As a countermeasure for missing block addresses, EP 0,670,555 A1 proposes the use of interpolation. Thus, if a block address fails to be detected, it is estimated by interpolation from neighboring block addresses. Meanwhile, EP 0,717,398 A2 (which corresponds to U.S. Ser. No. 08/571,776) proposes a system of affixing an error correction code to each address and, when error correction is not possible for a read out address data, estimating the address from neighboring addresses. With such a system, the rate of faulty code reproduction due to missing block data can be reduced if the address of an attentional block cannot be read out.
However, neither EP 0,670,555 A1 nor EP 0,717,398 A2 is satisfactory for instances where addresses are read out (and/or corrected) wrongly. If an address error occurs, the block data of that address can be read out as the data of some other address to make the code reproducing operation faulty.
In other words, there is a problem that the reliability or validity of the read out block addresses is not checked by a system according to either of the above patent documents.